Invention Grant
- Patent Title: Integrated circuit testing with power collapsed
- Patent Title (中): 集成电路测试与电源崩溃
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Application No.: US14172292Application Date: 2014-02-04
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Publication No.: US09267989B2Publication Date: 2016-02-23
- Inventor: Wei Chen , Yucong Tao , Matthew L. Severson , Jeffrey R. Gemar , Chang Yong Yang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Donald D. Min; Paul Holdaway
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/3177 ; G01R31/30 ; G01R31/3185

Abstract:
Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.
Public/Granted literature
- US20140223250A1 INTEGRATED CIRCUIT TESTING WITH POWER COLLAPSED Public/Granted day:2014-08-07
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