Invention Grant
US09269436B2 Techniques for determining victim row addresses in a volatile memory
有权
确定易失性存储器中的受害者行地址的技术
- Patent Title: Techniques for determining victim row addresses in a volatile memory
- Patent Title (中): 确定易失性存储器中的受害者行地址的技术
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Application No.: US14133011Application Date: 2013-12-18
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Publication No.: US09269436B2Publication Date: 2016-02-23
- Inventor: Sreenivas Mandava , Brian S. Morris , Suneeta Sah , Roy M. Stevens , Ted Rossin , Mathew W. Stefaniw , John H. Crawford
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Kacvinsky Daisak Bluni PLLC
- Main IPC: G11C7/02
- IPC: G11C7/02 ; G11C11/406 ; G06F12/10 ; G11C14/00
Abstract:
Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
Public/Granted literature
- US20140281207A1 Techniques for Determining Victim Row Addresses in a Volatile Memory Public/Granted day:2014-09-18
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