An impedance matching network comprises a first and a second signal terminal and a reference potential terminal. The network further comprises a first shunt branch between the first signal terminal and the reference potential terminal, the first shunt branch comprising a variable inductive element and a first capacitive element. The impedance matching network also comprises a second shunt branch between the second signal terminal and the reference potential terminal and comprising a second capacitive element. A series branch between the first signal terminal and the second signal terminal comprises a third capacitive element. Optionally, the first, second, and/or third capacitive element may be implemented as a variable capacitive element. The variable capacitive element comprises a plurality of transistors, wherein a combination of off-capacitances Coff of the transistors provide an overall capacitance of the variable capacitive element as a function of at least two independent transistor control signals.