Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.