公开(公告)号：US09281065B2

公开(公告)日：2016-03-08

申请号：US14456965

申请日：2014-08-11

Applicant: Empire Technology Development LLC

Inventor： Leonard Forbes

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7889

Abstract: Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.

Abstract translation: 对于配置有选择门的低功率非易失性存储器单元，一般描述了技术。 非易失性存储单元可以具有耦合到主体的晶体管本体，选择栅极和浮动栅极以及耦合到浮置栅极的控制栅极。 存储在浮动栅极上的电荷可以指示存储在存储单元上的数据，并且控制栅极可以被配置为调整存储在浮动栅极上的电荷。 选择栅极可以用于调整晶体管本体的状态以便于调整浮置栅极上的电荷，并且还可以用于使存储器单元对控制栅极不响应。

公开(公告)号：US20160042793A1

公开(公告)日：2016-02-11

申请号：US14456965

申请日：2014-08-11

Applicant: Empire Technology Development LLC

Inventor： Leonard Forbes

IPC: G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7889

Abstract: Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.

Abstract translation: 对于配置有选择门的低功率非易失性存储器单元，一般描述了技术。 非易失性存储单元可以具有耦合到主体的晶体管本体，选择栅极和浮动栅极以及耦合到浮置栅极的控制栅极。 存储在浮动栅极上的电荷可以指示存储在存储单元上的数据，并且控制栅极可以被配置为调整存储在浮动栅极上的电荷。 选择栅极可以用于调整晶体管本体的状态以便于调整浮置栅极上的电荷，并且还可以用于使存储器单元对控制栅极不响应。