Invention Grant
- Patent Title: Memory system with improved bus timing calibration
- Patent Title (中): 具有改进总线时序校准的存储系统
-
Application No.: US13939588Application Date: 2013-07-11
-
Publication No.: US09285828B2Publication Date: 2016-03-15
- Inventor: Roni Shoev , Yoav Kasorla
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F1/08
- IPC: G06F1/08 ; G06F1/10

Abstract:
A method includes communicating between a memory controller and multiple memory devices over an interface that includes at least a control signal and an information signal. For each memory device, a respective individual skew parameter, which is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device, is produced. The respective individual skew parameter is stored coupled to each memory device. The timing misalignment is corrected at the memory device using the stored individual timing skew.
Public/Granted literature
- US20150019899A1 MEMORY SYSTEM WITH IMPROVED BUS TIMING CALIBRATION Public/Granted day:2015-01-15
Information query