Invention Grant
US09285828B2 Memory system with improved bus timing calibration 有权
具有改进总线时序校准的存储系统

Memory system with improved bus timing calibration
Abstract:
A method includes communicating between a memory controller and multiple memory devices over an interface that includes at least a control signal and an information signal. For each memory device, a respective individual skew parameter, which is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device, is produced. The respective individual skew parameter is stored coupled to each memory device. The timing misalignment is corrected at the memory device using the stored individual timing skew.
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