A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply line; and a control circuit including a first constant current element, a first transistor, and a second transistor. In the control circuit, the first transistor has a gate coupled to the data line, one of a source and a drain coupled to the first constant current element, and the other one of the source and the drain coupled to the power supply line. The second transistor has a gate coupled to one of the source and the drain of the first transistor, one of a source and a drain coupled to the data line, and the other one of the source and the drain coupled to the control line.