Invention Grant
- Patent Title: Tiered access to on chip features
- Patent Title (中): 分层访问片上功能
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Application No.: US13799553Application Date: 2013-03-13
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Publication No.: US09292713B2Publication Date: 2016-03-22
- Inventor: Jason G. Sandri , Monib Ahmed , Ian S. Walker
- Applicant: Intel Corporation
- Applicant Address: US AZ Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US AZ Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F21/76
- IPC: G06F21/76 ; G06F21/10 ; H04L9/32 ; G06F21/85

Abstract:
In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access.
Public/Granted literature
- US20140283119A1 Tiered Access to On Chip Features Public/Granted day:2014-09-18
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