A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.