发明授权
- 专利标题: Circuit for low-power ternary domino reversible counting unit
- 专利标题(中): 低功率三元可逆计数单元电路
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申请号: US14797179申请日: 2015-07-12
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公开(公告)号: US09300290B1公开(公告)日: 2016-03-29
- 发明人: Pengjun Wang , Xuesong Zheng , Yuejun Zhang
- 申请人: Ningbo University
- 申请人地址: CN Ningbo
- 专利权人: NINGBO UNIVERSITY
- 当前专利权人: NINGBO UNIVERSITY
- 当前专利权人地址: CN Ningbo
- 代理机构: Matthias Scholl P.C.
- 代理商 Matthias Scholl
- 优先权: CN201410513510 20140929
- 主分类号: H03K19/00
- IPC分类号: H03K19/00 ; H03K19/0944
摘要:
A circuit for a ternary Domino reversible counting unit. The circuit includes a ternary adiabatic Domino D flip-flop, a ternary adiabatic Domino positive and negative circulation port, and a ternary adiabatic Domino T-operation circuit. The ternary adiabatic Domino T-operation circuit includes a first signal input end, a second signal input end, and a third signal input end, a selection signal input end, a signal output end, a first clock signal input end, and a second clock signal input end. The positive and negative circulation port includes a signal input end, a borrow terminal, a carry terminal, a first output end, a second output end, a first clock signal input end, a second clock signal input end, and a third clock signal input end. The D flip-flop includes a signal input end, a reset terminal, a set terminal, a reverse-phase set terminal, a signal output end.
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