Invention Grant
- Patent Title: Device isolation in FinFET CMOS
- Patent Title (中): FinFET CMOS器件隔离
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Application No.: US14599873Application Date: 2015-01-19
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Publication No.: US09305846B2Publication Date: 2016-04-05
- Inventor: Ajey Poovannummoottil Jacob , Murat Kerem Akarvardar , Steven Bentley , Toshiharu Nagumo , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz
- Applicant: GLOBALFOUNDRIES INC. , International Business Machines Corporation , Renesas Electronics Corporation
- Applicant Address: KY Grand Cayman US NY Armonk JP Nakahara-Ku
- Assignee: GlobalFoundries Inc.,International Business Machines Corporation,Renesas Electronics Corporation
- Current Assignee: GlobalFoundries Inc.,International Business Machines Corporation,Renesas Electronics Corporation
- Current Assignee Address: KY Grand Cayman US NY Armonk JP Nakahara-Ku
- Agency: Williams Morgan, P.C.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L29/06 ; H01L29/66 ; H01L21/8238 ; H01L21/761 ; H01L21/02 ; H01L21/266 ; H01L29/78

Abstract:
Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.
Public/Granted literature
- US20150140761A1 DEVICE ISOLATION IN FINFET CMOS Public/Granted day:2015-05-21
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