Invention Grant
- Patent Title: Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
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Application No.: US14024925Application Date: 2013-09-12
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Publication No.: US09305864B2Publication Date: 2016-04-05
- Inventor: Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
Public/Granted literature
- US20140008817A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT Public/Granted day:2014-01-09
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