Invention Grant
- Patent Title: Semiconductor apparatus with multi-layer capacitance structure
- Patent Title (中): 具有多层电容结构的半导体装置
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Application No.: US14445416Application Date: 2014-07-29
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Publication No.: US09305994B2Publication Date: 2016-04-05
- Inventor: Zhi-Biao Zhou , Shao-Hui Wu , Chi-Fa Ku
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsinchu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Agent Justin King
- Priority: CN201410247121 20140605
- Main IPC: H01L49/02
- IPC: H01L49/02

Abstract:
A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.
Public/Granted literature
- US20150357397A1 SEMICONDUCTOR APPARATUS Public/Granted day:2015-12-10
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