Invention Grant
- Patent Title: Method, apparatus and system for performing voltage margining
- Patent Title (中): 用于执行电压裕度的方法,装置和系统
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Application No.: US14140834Application Date: 2013-12-26
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Publication No.: US09317353B2Publication Date: 2016-04-19
- Inventor: Sanjay R. Ravi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G01R31/30 ; H04L25/49

Abstract:
In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.
Public/Granted literature
- US20150186197A1 METHOD, APPARATUS AND SYSTEM FOR PERFORMING VOLTAGE MARGINING Public/Granted day:2015-07-02
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