发明授权
US09318318B1 3D atomic layer gate or junction extender 有权
3D原子层门或连接扩展器

3D atomic layer gate or junction extender
摘要:
A method for fabricating a semiconductor device includes receiving a gated finned substrate comprising an isolation layer with a semiconductor fin formed thereon and a gate formed over the semiconductor fin, depositing an atomic layer of dopant on a portion of the semiconductor fin that is laterally adjacent to the gate, forming a lateral spacer on a sidewall of the gate and above a gate extension portion of the atomic layer of dopant, and epitaxially growing a raised source or drain region on the semiconductor fin, that is laterally adjacent to the lateral spacer, from the atomic layer of dopant. The method may also include conducting a low temperature annealing process to diffuse the atomic layer of dopant to the raised source or drain region of the semiconductor fin. A corresponding apparatus is also disclosed herein.
信息查询
0/0