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公开(公告)号:US10366918B2
公开(公告)日:2019-07-30
申请号:US15284956
申请日:2016-10-04
发明人: Kevin K. Chan , Sebastian U. Engelmann , Marinus Johannes Petrus Hopstaken , Christopher Scerbo , Hongwen Yan , Yu Zhu
IPC分类号: H01L21/223 , H01L21/768 , H01L23/535 , H01L29/20 , H01L29/66 , H01L21/28 , H01L29/78 , H01L29/207
摘要: After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.
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公开(公告)号:US10236366B2
公开(公告)日:2019-03-19
申请号:US15847177
申请日:2017-12-19
发明人: Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Jeng-Bang Yau
IPC分类号: H01L29/66 , H01L29/737 , H01L29/423 , H01L29/735 , H01L29/10
摘要: After forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer. An extrinsic base is then formed on top of the intrinsic base to fill a remaining volume of the trench by a deposition process.
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公开(公告)号:US10128343B2
公开(公告)日:2018-11-13
申请号:US15917484
申请日:2018-03-09
发明人: Kevin K. Chan , Cheng-Wei Cheng , Jack Oon Chu , Yanning Sun , Jeng-Bang Yau
IPC分类号: H01L29/41 , H01L29/08 , H01L29/20 , H01L29/45 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/3205 , H01L21/3213 , H01L21/283 , H01L29/201 , H01L21/285 , H01L21/02
摘要: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.
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公开(公告)号:US20180108778A1
公开(公告)日:2018-04-19
申请号:US15835849
申请日:2017-12-08
IPC分类号: H01L29/78 , H01L29/66 , H01L29/167 , H01L21/324 , H01L29/161 , H01L29/10 , H01L27/092 , H01L21/84 , H01L29/165
CPC分类号: H01L29/7851 , H01L21/324 , H01L21/845 , H01L27/0924 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
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公开(公告)号:US20180096893A1
公开(公告)日:2018-04-05
申请号:US15490414
申请日:2017-04-18
发明人: Takashi Ando , Kevin K. Chan , John Rozen , Jeng-Bang Yau , Yu Zhu
IPC分类号: H01L21/8234 , H01L29/66 , H01L21/02 , H01L21/18 , H01L21/3215
CPC分类号: H01L21/823418 , H01L21/02241 , H01L21/02546 , H01L21/0257 , H01L21/18 , H01L21/2233 , H01L21/2236 , H01L21/28575 , H01L21/3215 , H01L29/0847 , H01L29/20 , H01L29/452 , H01L29/66007 , H01L29/66522 , H01L29/6659 , H01L29/66628
摘要: A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.
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公开(公告)号:US20170263702A1
公开(公告)日:2017-09-14
申请号:US15604719
申请日:2017-05-25
IPC分类号: H01L29/06 , H01L21/34 , H01L29/66 , H01L29/78 , H01L21/311 , H01L21/321
CPC分类号: H01L29/0649 , H01L21/0262 , H01L21/31111 , H01L21/32105 , H01L21/34 , H01L21/38 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
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公开(公告)号:US09752251B2
公开(公告)日:2017-09-05
申请号:US13862759
申请日:2013-04-15
发明人: Kevin K. Chan , Eric C. Harley , Yue Ke , Annie Levesque
CPC分类号: C30B25/04 , C30B25/14 , C30B29/52 , H01L21/0243 , H01L21/02433 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/845 , H01L29/66795
摘要: A self-limiting selective epitaxy process can be employed on a plurality of semiconductor fins such that the sizes of raised active semiconductor regions formed by the selective epitaxy process are limited to dimensions determined by the sizes of the semiconductor fins. Specifically, the self-limiting selective epitaxy process limits growth of the semiconductor material along directions that are perpendicular to crystallographic facets formed during the selective epitaxy process. Once the crystallographic facets become adjoined to one another or to a dielectric surface, growth of the semiconductor material terminates, thereby preventing merger among epitaxially deposited semiconductor materials.
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公开(公告)号:US09691886B2
公开(公告)日:2017-06-27
申请号:US14984575
申请日:2015-12-30
发明人: Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Jeng-Bang Yau
IPC分类号: H01L29/737 , H01L29/10 , H01L29/08 , H01L27/082 , H01L27/12 , H01L29/16 , H01L29/66 , H01L29/735 , H01L21/762 , H01L29/165 , H01L29/73
CPC分类号: H01L29/737 , H01L21/76283 , H01L27/082 , H01L27/1203 , H01L29/0808 , H01L29/0817 , H01L29/0821 , H01L29/1008 , H01L29/16 , H01L29/165 , H01L29/66242 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735
摘要: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.
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公开(公告)号:US09673307B1
公开(公告)日:2017-06-06
申请号:US15097548
申请日:2016-04-13
发明人: Kevin K. Chan , Pouya Hashemi , Tak H. Ning , Alexander Reznicek
IPC分类号: H01L29/66 , H01L29/735 , H01L23/31 , H01L29/161 , H01L29/20 , H01L29/10 , H01L29/08 , H01L29/737 , H01L29/165 , H01L29/04 , H01L29/06 , H01L23/29 , H01L21/683 , H01L21/02 , H01L21/308 , H01L21/265
CPC分类号: H01L29/0808 , H01L21/02172 , H01L21/02381 , H01L21/02532 , H01L21/02595 , H01L21/26513 , H01L21/26586 , H01L21/3081 , H01L21/6835 , H01L21/74 , H01L23/291 , H01L23/298 , H01L23/3171 , H01L29/04 , H01L29/0623 , H01L29/0649 , H01L29/0821 , H01L29/1008 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/66242 , H01L29/6625 , H01L29/735 , H01L29/737 , H01L2221/6835
摘要: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
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公开(公告)号:US20170092749A1
公开(公告)日:2017-03-30
申请号:US14867384
申请日:2015-09-28
发明人: Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Jeng-Bang Yau
IPC分类号: H01L29/737 , H01L29/66 , H01L29/06
CPC分类号: H01L29/737 , H01L29/1008 , H01L29/42304 , H01L29/66242 , H01L29/6625 , H01L29/735
摘要: After forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer. An extrinsic base is then formed on top of the intrinsic base to fill a remaining volume of the trench by a deposition process.
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