Invention Grant
- Patent Title: Method and layout of an integrated circuit
- Patent Title (中): 集成电路的方法和布局
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Application No.: US14341130Application Date: 2014-07-25
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Publication No.: US09323881B2Publication Date: 2016-04-26
- Inventor: Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Ruei-Wun Sun , Hung-Jung Tseng , Shun Li Chen , Li-Chun Tien
- Applicant: Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Ruei-Wun Sun , Hung-Jung Tseng , Shun Li Chen , Li-Chun Tien
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Hauptman Ham, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/482

Abstract:
An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
Public/Granted literature
- US20140332971A1 METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT Public/Granted day:2014-11-13
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