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    Method and layout of an integrated circuit
    1.
    发明授权
    Method and layout of an integrated circuit 有权
    集成电路的方法和布局

    公开(公告)号：US09323881B2

    公开(公告)日：2016-04-26

    申请号：US14341130

    申请日：2014-07-25

    申请人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Ruei-Wun Sun ,  Hung-Jung Tseng ,  Shun Li Chen ,  Li-Chun Tien

    发明人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Ruei-Wun Sun ,  Hung-Jung Tseng ,  Shun Li Chen ,  Li-Chun Tien

    IPC分类号： G06F17/50 ,  H01L23/482

    CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.

    摘要翻译： 集成电路布局包括P型有源区和N型有源区，以及多个树干。 集成电路布局还包括连接到P型有源区的第一金属连接; 以及连接到N型有源区的第二金属连接。 多个树干的每个中继线与第一金属连接和第二金属连接电连接。 多个树干的每个树干基本上垂直于第一金属连接和第二金属连接。 多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度。

    METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
    2.
    发明申请
    METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
    集成电路的方法和布局

    公开(公告)号：US20140332971A1

    公开(公告)日：2014-11-13

    申请号：US14341130

    申请日：2014-07-25

    申请人： Hsiang-Jen TSENG ,  Ting-Wei CHIANG ,  Wei-Yu CHEN ,  Ruei-Wun SUN ,  Hung-Jung TSENG ,  Shun Li CHEN ,  Li-Chun TIEN

    发明人： Hsiang-Jen TSENG ,  Ting-Wei CHIANG ,  Wei-Yu CHEN ,  Ruei-Wun SUN ,  Hung-Jung TSENG ,  Shun Li CHEN ,  Li-Chun TIEN

    IPC分类号： G06F17/50 ,  H01L23/482

    CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.

    摘要翻译： 集成电路布局包括P型有源区和N型有源区，以及多个树干。 集成电路布局还包括连接到P型有源区的第一金属连接; 以及连接到N型有源区的第二金属连接。 多个树干的每个中继线与第一金属连接和第二金属连接电连接。 多个树干的每个树干基本上垂直于第一金属连接和第二金属连接。 多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度。

    METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
    4.
    发明申请
    METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
    集成电路的方法和布局

    公开(公告)号：US20140195997A1

    公开(公告)日：2014-07-10

    申请号：US13778912

    申请日：2013-02-27

    申请人： Hsiang-Jen TSENG ,  Ting-Wei CHIANG ,  Wei-Yu CHEN ,  Ruei-Wun SUN ,  Hung-Jung TSENG ,  Shun Li CHEN ,  Li-Chun TIEN

    发明人： Hsiang-Jen TSENG ,  Ting-Wei CHIANG ,  Wei-Yu CHEN ,  Ruei-Wun SUN ,  Hung-Jung TSENG ,  Shun Li CHEN ,  Li-Chun TIEN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.

    摘要翻译： 集成电路布局包括P型有源区，N型有源区，第一金属连接，第二金属连接和多个树干。 多个树干基本并排地形成并且彼此平行。 第一金属连接基本上设置在P型有源区上，并且与P型有源区中的PMOS晶体管的漏极区域电连接。 第二金属连接基本上设置在N型有源区上，并且与N型有源区中的NMOS晶体管的漏区电连接。 多个树干电连接并且基本上垂直于第一金属连接和第二金属连接。 多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度，并且布置成位于两组树干之间。

    Voltage level shifter with single well voltage
    5.
    发明申请
    Voltage level shifter with single well voltage 有权
    具有单井电压的电压电平转换器

    公开(公告)号：US20080143418A1

    公开(公告)日：2008-06-19

    申请号：US11639006

    申请日：2006-12-14

    申请人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

    发明人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

    IPC分类号： H03L5/00

    CPC分类号： H03K3/35613

    摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

    摘要翻译： 本发明公开了一种电压电平转换器，它包括具有栅极，源极和体耦合到输入端的第一P型金属氧化物半导体（PMOS）晶体管，第一正电压电源和第二正电压 电源，以及分别具有源极，漏极和体耦合到第三正电压电源，输出节点和第二正电压电源的第二PMOS晶体管，其中形成第一和第二PMOS晶体管 在一个Nwell。

    Method and layout of an integrated circuit
    6.
    发明授权
    Method and layout of an integrated circuit 有权
    集成电路的方法和布局

    公开(公告)号：US08819610B2

    公开(公告)日：2014-08-26

    申请号：US13778912

    申请日：2013-02-27

    申请人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Ruei-Wun Sun ,  Hung-Jung Tseng ,  Shun Li Chen ,  Li-Chun Tien

    发明人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Ruei-Wun Sun ,  Hung-Jung Tseng ,  Shun Li Chen ,  Li-Chun Tien

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.

    摘要翻译： 集成电路布局包括P型有源区，N型有源区，第一金属连接，第二金属连接和多个树干。 多个树干基本并排地形成并且彼此平行。 第一金属连接基本上设置在P型有源区上，并且与P型有源区中的PMOS晶体管的漏极区域电连接。 第二金属连接基本上设置在N型有源区上，并且与N型有源区中的NMOS晶体管的漏区电连接。 多个树干电连接并且基本上垂直于第一金属连接和第二金属连接。 多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度，并且布置成位于两组树干之间。