Invention Grant
US09324828B2 Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming
有权
垂直P型，N型，P型（PNP）结集成电路（IC）结构和成型方法
- Patent Title: Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming
- Patent Title (中): 垂直P型，N型，P型（PNP）结集成电路（IC）结构和成型方法
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Application No.: US14457524Application Date: 2014-08-12
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Publication No.: US09324828B2Publication Date: 2016-04-26
- Inventor: Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Steven J. Meyers
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L29/66 ; H01L29/732 ; H01L29/10 ; H01L21/768
Abstract:
Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.
Public/Granted literature
- US20160049492A1 VERTICAL P-TYPE, N-TYPE, P-TYPE (PNP) JUNCTION INTEGRATED CIRCUIT (IC) STRUCTURE, AND METHODS OF FORMING Public/Granted day:2016-02-18
Information query
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