Invention Grant
- Patent Title: SerDes PVT detection and closed loop adaptation
- Patent Title (中): SerDes PVT检测和闭环适配
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Application No.: US14244474Application Date: 2014-04-03
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Publication No.: US09325537B2Publication Date: 2016-04-26
- Inventor: Mohammad S. Mobin , Weiwei Mao , Chintan M. Desai , Freeman Y. Zhong , Ye Liu
- Applicant: LSI Corporation
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H04L27/08
- IPC: H04L27/08 ; H04L25/03 ; H04L25/06

Abstract:
In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.
Public/Granted literature
- US20150249555A1 SERDES PVT DETECTION AND CLOSED LOOP ADAPTATION Public/Granted day:2015-09-03
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