A high-voltage circuit is described that comprises a high-voltage finFET can have a semiconductor fin with an insulating cap on the fin. A gate dielectric is disposed on the first and second sides of the fin. A gate overlies the gate dielectric and a channel region in the fin on the first and second sides, and over the cap. Source/drain terminals are disposed on opposing sides of the gate in the fin, and can include lightly doped regions that extend away from the edge of the gate to more highly doped contacts. The dimensions of the structures can be configured so that the transistor has a breakdown voltage of 30 V or higher.