Invention Grant
US09343320B2 Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins
有权
eDRAM和具有一次性填充的逻辑器件的图案因子依赖性减轻以缓解与鳍片的深沟槽集成
- Patent Title: Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins
- Patent Title (中): eDRAM和具有一次性填充的逻辑器件的图案因子依赖性减轻以缓解与鳍片的深沟槽集成
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Application No.: US14098650Application Date: 2013-12-06
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Publication No.: US09343320B2Publication Date: 2016-05-17
- Inventor: Kangguo Cheng , Joseph Ervin , Juntao Li , Chengwen Pei , Geng Wang
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully Scott Murphy and Presser
- Agent Frank Digiglio
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/306 ; H01L21/308 ; H01L21/768 ; H01L21/3205 ; H01L21/84 ; H01L29/66 ; H01L29/94 ; H01L27/12

Abstract:
Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench.
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