- Patent Title: Wafer level semiconductor package and manufacturing methods thereof
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Application No.: US14577942Application Date: 2014-12-19
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Publication No.: US09343333B2Publication Date: 2016-05-17
- Inventor: John Richard Hunt
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu; Angela D. Murch
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/48 ; H01L21/56 ; H01L23/29 ; H01L23/31 ; H01L23/498 ; H01L23/00 ; H01L25/10
Abstract:
A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.
Public/Granted literature
- US20150140737A1 WAFER LEVEL SEMICONDUCTOR PACKAGE AND MANUFACTURING METHODS THEREOF Public/Granted day:2015-05-21
Information query
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