发明授权
US09349484B2 Sample-and-hold circuit for an interleaved analog-to-digital converter
有权
用于交错模数转换器的采样和保持电路
- 专利标题: Sample-and-hold circuit for an interleaved analog-to-digital converter
- 专利标题(中): 用于交错模数转换器的采样和保持电路
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申请号: US14808267申请日: 2015-07-24
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公开(公告)号: US09349484B2公开(公告)日: 2016-05-24
- 发明人: Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
- 申请人: IMEC VZW
- 申请人地址: BE Leuven
- 专利权人: IMEC VZW
- 当前专利权人: IMEC VZW
- 当前专利权人地址: BE Leuven
- 代理机构: McDonnell Boehnen Hulbert & Berghoff LLP
- 优先权: EP14178665 20140725
- 主分类号: H03M1/00
- IPC分类号: H03M1/00 ; G11C27/02 ; H03M1/12
摘要:
The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
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