Invention Grant
- Patent Title: Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
- Patent Title (中): 栅极电介质结构的厚度缩小方法,形成集成电路的方法以及集成电路
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Application No.: US14080533Application Date: 2013-11-14
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Publication No.: US09349823B2Publication Date: 2016-05-24
- Inventor: Kisik Choi
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/51 ; H01L27/092 ; H01L21/8234 ; H01L21/8238

Abstract:
Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.
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