An array substrate includes a unit pixel group having first and second sub-pixel rows. The array substrate includes a plurality of gate lines extending along a first direction and adjacent to each other on a base substrate, a plurality of gate electrodes electrically coupled to the gate lines, a plurality of semiconductor patterns overlapping the gate electrodes, a plurality of data lines extending along a second direction and electrically coupled to first portions of the semiconductor patterns, a plurality of drain electrode patterns electrically coupled to second portions of the semiconductor patterns, and a plurality of pixel electrodes electrically coupled to the drain electrodes. The second portion of the semiconductor pattern spaced from the first portion thereof. The gate lines and the data lines are bent. Sub-pixels in the first sub-pixel row have opening areas that are different in size than that of sub-pixels in the second sub-pixel row.