A method is described that includes performing the following with an instruction execution pipeline of a semiconductor chip. Multiplying two vectors by: receiving a vector element multiplicand and vector element multiplier expressed in a first base system; converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying with a first execution unit of the pipeline the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result; accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and, converting contents of the register into the first base system.