Invention Grant
- Patent Title: FinFET spacer etch for eSiGe improvement
- Patent Title (中): FinFET间隔蚀刻用于eSiGe改进
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Application No.: US13918622Application Date: 2013-06-14
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Publication No.: US09356147B2Publication Date: 2016-05-31
- Inventor: Hong Yu , Hyucksoo Yang , Puneet Khanna
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L29/66

Abstract:
A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.
Public/Granted literature
- US20140367751A1 FINFET SPACER ETCH FOR eSiGe IMPROVEMENT Public/Granted day:2014-12-18
Information query
IPC分类: