公开(公告)号：US09099380B2

公开(公告)日：2015-08-04

申请号：US14511811

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy Vakada ,  Laegu Kang ,  Michael P. Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/167 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。

公开(公告)号：US20140370697A1

公开(公告)日：2014-12-18

申请号：US13919645

申请日：2013-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Puneet Khanna

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract translation: 公开了用于打开用于替换栅极工艺的多晶硅NFET和PFET栅极的方法。 实施例包括提供具有氮化物盖的多晶硅栅极; 限定多晶硅栅极的PFET和NFET区域，在氮化物盖上形成氮化物凸块; 用PMD将氮化物盖覆盖到氮化物凸块的顶部; 对PMD和氮化物凸块进行1：1干蚀刻; 以及对氮化物帽进行选择性的第二干蚀刻，直到多晶硅栅极的顶表面。 其他实施例包括在氮化物盖上形成氮化物凸块之后，使PMD凹陷以暴露氮化物盖; 用氮化物填料覆盖氮化物盖和氮化物凸块，形成平面氮化物表面; 并且将氮化物填充物，氮化物凸块和氮化物帽向下移动到多晶硅栅极。

公开(公告)号：US09356147B2

公开(公告)日：2016-05-31

申请号：US13918622

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Puneet Khanna

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.

Abstract translation: 通过在传统的间隔物ME步骤之后直接插入Si凹陷步骤和所得到的器件来蚀刻FinFET间隔物的方法。 实施例包括在具有硅翅片的基板上形成栅极，栅极在其上表面具有氮化物盖，在氮化物盖的上表面上具有氧化物盖; 在所述硅片和所述栅极上形成介电层; 从所述氧化物盖的上表面和所述硅片的上表面去除所述电介质层; 凹陷硅片; 并且从硅片和剩余的硅片的侧表面去除电介质层。

公开(公告)号：US20160035630A1

公开(公告)日：2016-02-04

申请号：US14882640

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

Abstract translation: 本文公开的一种说明性方法包括执行第一多个外延沉积工艺，以在掩蔽P活性区域的同时，选择性地在N活性区域上方形成第一多个半导体材料，进行第二多个外延沉积工艺以形成第二多个 半导体材料选择性地在P有源区上方，同时掩蔽N有源区，在N-有源区中和上方形成N型晶体管，并在P-活性区中和上方形成P型晶体管。

公开(公告)号：US20180047641A1

公开(公告)日：2018-02-15

申请号：US15792357

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

公开(公告)号：US09362357B2

公开(公告)日：2016-06-07

申请号：US14716045

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laegu Kang ,  Vara Govindeswara Reddy Vakada ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/165

CPC classification number: H01L29/0692 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66651

Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

公开(公告)号：US09209181B2

公开(公告)日：2015-12-08

申请号：US13918536

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

Abstract translation: 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

公开(公告)号：US08927356B1

公开(公告)日：2015-01-06

申请号：US13919645

申请日：2013-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Puneet Khanna

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L21/823828 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract translation: 公开了用于打开用于替换栅极工艺的多晶硅NFET和PFET栅极的方法。 实施例包括提供具有氮化物盖的多晶硅栅极; 限定多晶硅栅极的PFET和NFET区域，在氮化物盖上形成氮化物凸块; 用PMD将氮化物盖覆盖到氮化物凸块的顶部; 对PMD和氮化物凸块进行1：1干蚀刻; 以及对氮化物帽进行选择性的第二干蚀刻，直到多晶硅栅极的顶表面。 其他实施例包括在氮化物盖上形成氮化物凸块之后，使PMD凹陷以暴露氮化物盖; 用氮化物填料覆盖氮化物盖和氮化物凸块，形成平面氮化物表面; 并且将氮化物填充物，氮化物凸块和氮化物帽向下移动到多晶硅栅极。

公开(公告)号：US08916442B2

公开(公告)日：2014-12-23

申请号：US13743886

申请日：2013-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy Vakada ,  Laegu Kang ,  Michael P. Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。

公开(公告)号：US10483172B2

公开(公告)日：2019-11-19

申请号：US15792357

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/82 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.