Invention Grant
- Patent Title: Three channel cache-coherency socket protocol
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Application No.: US14859340Application Date: 2015-09-20
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Publication No.: US09361230B2Publication Date: 2016-06-07
- Inventor: Jean-Jacques Lecler
- Applicant: QUALCOMM Technologies Inc.
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Technologies, Inc.
- Current Assignee: Qualcomm Technologies, Inc.
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F13/42 ; G06F3/06

Abstract:
A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.
Public/Granted literature
- US20160011976A1 THREE CHANNEL CACHE-COHERENCY SOCKET PROTOCOL Public/Granted day:2016-01-14
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