Invention Grant
- Patent Title: Constrained placement of connected elements
- Patent Title (中): 连接元素的约束位置
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Application No.: US14453585Application Date: 2014-08-06
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Publication No.: US09361419B2Publication Date: 2016-06-07
- Inventor: Robert L. Blair , Daniel A. Risler , A Martin Mallinson
- Applicant: ESS Technology, Inc.
- Applicant Address: US CA Milpitas
- Assignee: ESS Technology, Inc.
- Current Assignee: ESS Technology, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Gard & Kaslow LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02

Abstract:
An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.
Public/Granted literature
- US20150046894A1 Constrained Placement of Connected Elements Public/Granted day:2015-02-12
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