Invention Grant
US09361419B2 Constrained placement of connected elements 有权
连接元素的约束位置

Constrained placement of connected elements
Abstract:
An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.
Public/Granted literature
Information query
Patent Agency Ranking
0/0