发明授权
- 专利标题： Tuning gate lengths in semiconductor device structures
- 专利标题（中）： 调整半导体器件结构中的栅极长度
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申请号： US14624864申请日： 2015-02-18
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公开(公告)号： US09362354B1公开(公告)日： 2016-06-07
- 发明人: Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
- 申请人： International Business Machines Corporation
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 代理机构： Cantor Colburn LLP
- 代理商 Vazken Alexanian
- 主分类号： H01L21/84
- IPC分类号： H01L21/84 ; H01L29/06 ; H01L21/02 ; H01L29/66 ; H01L29/41
摘要：
A method for tuning gate lengths in nanowire semiconductor device structures. The present invention tunes the gate length by having the suspension height of the nanowire channels altered. The first method alters the suspension height by offsetting the height of the nanowires while utilizing gates of similar tapered dimensions, such that the nanowires pass through the gate regions at different heights and result in different gate length nanowire transistor device structures. The second method alters the suspension height by offsetting the height of the steps that the gates of similar tapered dimensions are formed on, such that the nanowires pass through the gate regions at different heights, resulting in different gate length nanowire transistor device structures. Both methods facilitate a decrease in overall fabrication costs by allowing the same type of patterned gate stacks to be used in order to produce channels of various lengths.
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