Forming interconnect features with reduced sidewall tapering

Invention Grant

US09373543B1 Forming interconnect features with reduced sidewall tapering 有权

Title translation: 形成互连功能，减少侧壁渐缩

Please log in to see more content

Patent Title: Forming interconnect features with reduced sidewall tapering
Patent Title (中): 形成互连功能，减少侧壁渐缩
Application No.: US14876023

Application Date: 2015-10-06
Publication No.: US09373543B1

Publication Date: 2016-06-21
Inventor: Frank W. Mont , Shariq Siddiqui , Douglas M. Trickett , Brown Cornelius Peethala
Applicant: GLOBALFOUNDRIES Inc. , International Business Machines Corporation
Applicant Address: KY Grand Cayman US NY Armonk
Assignee: GLOBALFOUNDRIES Inc.,International Business Machines Corporation
Current Assignee: GLOBALFOUNDRIES Inc.,International Business Machines Corporation
Current Assignee Address: KY Grand Cayman US NY Armonk
Agency: Amerson Law Firm, PLLC
Main IPC: H01L21/4763
IPC: H01L21/4763 ; H01L21/768 ; H01L21/311

Forming interconnect features with reduced sidewall tapering

Abstract:

A method includes forming a stack of materials including a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer positioned above the first dielectric layer. An etch mask including a plurality of spaced apart mask elements is formed above the second dielectric layer. The mask elements define at least a first via opening exposing the second dielectric layer. A patterning layer is formed above the etch mask. A second via opening is formed in the patterning layer to expose the first via opening in the etch mask. The second dielectric layer is etched through the second via opening to define a third via opening in the second dielectric layer exposing the conductive feature. The patterning layer and the etch mask are removed. A conductive via contacting the conductive feature is formed in the third via opening.

Abstract(Chinese):

一种方法包括形成包括其中定位有导电特征的第一介电层的材料堆叠和位于第一介电层上方的第二介电层。包括多个间隔开的掩模元件的蚀刻掩模形成在第二介电层的上方。掩模元件至少限定了暴露第二介电层的第一通孔。在蚀刻掩模上方形成图形层。在图案化层中形成第二通孔，以露出蚀刻掩模中的第一通孔。通过第二通孔开口蚀刻第二电介质层，以在暴露导电特征的第二电介质层中限定第三通孔。图案化层和蚀刻掩模被去除。在第三通孔中形成有与导电特征接触的导电通路。

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）