Invention Grant
- Patent Title: Flat no-lead packages with electroplated edges
- Patent Title (中): 带电镀边缘的扁平无铅封装
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Application No.: US14842460Application Date: 2015-09-01
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Publication No.: US09373569B1Publication Date: 2016-06-21
- Inventor: Reynaldo Corpuz Javier , Alok Kumar Lohia , Andy Quang Tran
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATION
- Current Assignee: TEXAS INSTRUMENTS INCORPORATION
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; Frank D. Cimino
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/495 ; H01L21/48 ; H01L21/56 ; H01L21/78 ; H01L23/31

Abstract:
A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad and exposed back sides of the terminals. Partial sawing in saw lanes begins from the back side through the terminals terminating within the plastic encapsulation to provide exposed side walls of the terminals and of the plastic encapsulation. The exposed thermal pad and exposed back side of the terminals are all shorted together to form exposed electrically interconnected metal surfaces (interconnected surfaces). The interconnected surfaces are electroplated with a solder wetable metal or metal alloy plating layer. The interconnected surfaces are decoupled. A second sawing in the saw lanes finishes sawing through the plastic encapsulation to provide singulation, forming a plurality of packaged semiconductor devices.
Information query
IPC分类: