Invention Grant
- Patent Title: Integrated oxide recess and floating gate fin trimming
- Patent Title (中): 集成氧化物凹槽和浮栅鳍片修整
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Application No.: US14448901Application Date: 2014-07-31
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Publication No.: US09378978B2Publication Date: 2016-06-28
- Inventor: Vinod R. Purayath , Randhir Thakur , Shankar Venkataraman , Nitin K. Ingle
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/3213
- IPC: H01L21/3213 ; H01L21/28 ; H01L29/40 ; H01L29/423 ; H01L21/677

Abstract:
Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.
Public/Granted literature
- US20160035586A1 INTEGRATED OXIDE RECESS AND FLOATING GATE FIN TRIMMING Public/Granted day:2016-02-04
Information query
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