Invention Grant
- Patent Title: Parallel processing for low latency network address translation
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Application No.: US14808149Application Date: 2015-07-24
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Publication No.: US09379978B2Publication Date: 2016-06-28
- Inventor: Alessandro Fulli , Putu Harry Subagio , Chih-Tsung Huang
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Edell, Shapiro & Finnan, LLC
- Main IPC: H04L12/745
- IPC: H04L12/745 ; H04L12/741 ; H04L29/06 ; H04L29/12 ; H04L12/727

Abstract:
A packet is received at an ingress port of a networking device and a forwarding result that identifies an egress port for the packet is generated. In parallel with the generation of the forwarding result, a network address translation (NAT) result that identifies one or more NAT rules for possible application to the packet is generated. The forwarding result and the NAT result are then used to generate a routing decision result.
Public/Granted literature
- US20150334020A1 Parallel Processing for Low Latency Network Address Translation Public/Granted day:2015-11-19
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