Invention Grant
US09385052B2 Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
有权
半导体器件和在载体上形成叠层互连结构的方法,用于在临时阶段进行测试
- Patent Title: Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
- Patent Title (中): 半导体器件和在载体上形成叠层互连结构的方法,用于在临时阶段进行测试
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Application No.: US13832118Application Date: 2013-03-15
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Publication No.: US09385052B2Publication Date: 2016-07-05
- Inventor: Yaojian Lin , Kang Chen
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates; P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/56 ; H01L23/498 ; H01L23/28 ; H01L23/00 ; H01L25/10 ; H01L23/31 ; H01L23/538

Abstract:
A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.
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