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US09385124B1 Methods of forming reduced thickness spacers in CMOS based integrated circuit products 有权
在基于CMOS的集成电路产品中形成厚度减薄的方法

Methods of forming reduced thickness spacers in CMOS based integrated circuit products
Abstract:
One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.
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