Invention Grant
US09385124B1 Methods of forming reduced thickness spacers in CMOS based integrated circuit products
有权
在基于CMOS的集成电路产品中形成厚度减薄的方法
- Patent Title: Methods of forming reduced thickness spacers in CMOS based integrated circuit products
- Patent Title (中): 在基于CMOS的集成电路产品中形成厚度减薄的方法
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Application No.: US14845499Application Date: 2015-09-04
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Publication No.: US09385124B1Publication Date: 2016-07-05
- Inventor: Wen Pin Peng , Min-hwa Chi , Garo Jacques Derderian
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/092 ; H01L21/8238 ; H01L21/311 ; H01L29/66 ; H01L21/02 ; H01L29/78 ; H01L29/165

Abstract:
One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.
Information query
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