Invention Grant
US09385233B2 Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
有权
具有部分电介质隔离的散装finFET,其特征在于在氧化物下方具有穿通停止层
- Patent Title: Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
- Patent Title (中): 具有部分电介质隔离的散装finFET,其特征在于在氧化物下方具有穿通停止层
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Application No.: US13927698Application Date: 2013-06-26
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Publication No.: US09385233B2Publication Date: 2016-07-05
- Inventor: Murat K. Akarvardar , Ajey P. Jacob
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries Inc.
- Current Assignee: GlobalFoundries Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/165

Abstract:
A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.
Public/Granted literature
- US20150001591A1 BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THROUGH STOPPING LAYER UNDER THE OXIDE Public/Granted day:2015-01-01
Information query
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