A memory device includes a substrate, a first doped region, composite structures, word lines, and a charge storage layer. The first doped region is disposed on a surface of the substrate. The composite structures are disposed on the first doped region. Each composite structure includes two semiconductor fin structures and a dielectric layer. Each semiconductor fin structure includes a second doped region disposed at an upper portion of the semiconductor fin structure and a body region disposed between the second doped region and the first doped region. The dielectric layer is disposed between the semiconductor fin structures. The word lines are disposed on the substrate. Each word line covers a partial sidewall and a partial top of each composite structure. The charge storage layer is disposed between the composite structures and the word lines.