公开(公告)号：US12237024B2

公开(公告)日：2025-02-25

申请号：US17894838

申请日：2022-08-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Kun-Tse Lee ,  Han-Sung Chen ,  Shih-Chang Huang

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/34

Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

公开(公告)号：US12224038B2

公开(公告)日：2025-02-11

申请号：US18191903

申请日：2023-03-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuan-Chih Chen ,  Chia-Hong Lee ,  Ming-Hsiu Lee

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/54

Abstract: A memory device and an intelligent operation method thereof are provided. The memory device includes a memory array, a signal generating circuit, an environment detecting circuit and an artificial intelligence (AI) circuit. The signal generating circuit is configured to generate an inputting signal. The environment detecting circuit is configured to detect at least one environment information. The AI circuit is connected among the memory array, the signal generating circuit and the environment detecting circuit. The AI circuit at least receives the inputting signal from the signal generating circuit, receives the environment information from the environment detecting circuit, receives a first performance information from the memory array, receives a second performance information from the AI circuit and outputs an ideal signal to the memory array according to the inputting signal, the environment information, the first performance information and the second performance information.

公开(公告)号：US12205894B2

公开(公告)日：2025-01-21

申请号：US17697074

申请日：2022-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang ,  Yun-Chu Lin

IPC: H01L23/528

Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

公开(公告)号：US20250022508A1

公开(公告)日：2025-01-16

申请号：US18903041

申请日：2024-10-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE ,  Ming-Hsiu LEE

IPC: G11C13/00 ,  G06F7/544

Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

公开(公告)号：US12198770B2

公开(公告)日：2025-01-14

申请号：US17988773

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Chen-Huan Chen ,  Ken-Hui Chen

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

公开(公告)号：US12198752B2

公开(公告)日：2025-01-14

申请号：US18206422

申请日：2023-06-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Cheng-Lin Sung ,  Yung-Feng Lin

IPC: G11C16/28 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US12197745B2

公开(公告)日：2025-01-14

申请号：US17817711

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06

Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

公开(公告)号：US20250014635A1

公开(公告)日：2025-01-09

申请号：US18347571

申请日：2023-07-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Hao Tseng ,  Shao Yu Fang

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

Abstract: An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

公开(公告)号：US20240414921A1

公开(公告)日：2024-12-12

申请号：US18331805

申请日：2023-06-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

公开(公告)号：US12160990B2

公开(公告)日：2024-12-03

申请号：US17678287

申请日：2022-02-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jung-Yi Guo ,  Chun-Min Cheng

IPC: H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10

Abstract: A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.