Invention Grant
US09389871B2 Combined floating point multiplier adder with intermediate rounding logic
有权
具有中间舍入逻辑的组合浮点乘法器加法器
- Patent Title: Combined floating point multiplier adder with intermediate rounding logic
- Patent Title (中): 具有中间舍入逻辑的组合浮点乘法器加法器
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Application No.: US13840363Application Date: 2013-03-15
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Publication No.: US09389871B2Publication Date: 2016-07-12
- Inventor: Marc Lupon , Grigorios Magklis , Sridhar Samudrala , Raul Martinez , Kyriakos A. Stavrou , Enric Gibert Codina
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F9/455

Abstract:
An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.
Public/Granted literature
- US20140281419A1 COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING LOGIC Public/Granted day:2014-09-18
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