Invention Grant
US09389871B2 Combined floating point multiplier adder with intermediate rounding logic 有权
具有中间舍入逻辑的组合浮点乘法器加法器

Combined floating point multiplier adder with intermediate rounding logic
Abstract:
An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.
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