Techniques described herein are generally related to managing cached memory addresses in a multi-core processor device that has a plurality of cores and a plurality of caches. Communication between the plurality of caches of and a main memory may be monitored. One or more memory addresses cached by the plurality of cores may be identified based on the monitored communications. A probabilistic memory address distribution table of the locations of the one or more memory addresses cached by the plurality of core may be generated and location of a given memory address can be predicted based upon the probabilistic memory address distribution table.