公开(公告)号：US20150242322A1

公开(公告)日：2015-08-27

申请号：US14369913

申请日：2013-08-12

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Sriram Vajapeyam

IPC: G06F12/08 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F12/0842 ,  G06F11/3006 ,  G06F11/3404 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/62

Abstract: Techniques described herein are generally related to managing cached memory addresses in a multi-core processor device that has a plurality of cores and a plurality of caches. Communication between the plurality of caches of and a main memory may be monitored. One or more memory addresses cached by the plurality of cores may be identified based on the monitored communications. A probabilistic memory address distribution table of the locations of the one or more memory addresses cached by the plurality of core may be generated and location of a given memory address can be predicted based upon the probabilistic memory address distribution table.

Abstract translation: 本文描述的技术通常涉及在具有多个核心和多个高速缓存的多核心处理器设备中管理高速缓存的存储器地址。 可以监视多个高速缓存之间的通信和主存储器。 可以基于所监视的通信来识别由多个核心高速缓存的一个或多个存储器地址。 可以生成由多个核心缓存的一个或多个存储器地址的位置的概率存储器地址分布表，并且可以基于概率存储器地址分布表来预测给定存储器地址的位置。

公开(公告)号：US20150234687A1

公开(公告)日：2015-08-20

申请号：US14128477

申请日：2013-06-11

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Sriram Vajapeyam

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/5088 ,  G06F9/4856 ,  G06F11/3006 ,  G06F11/3433

Abstract: Techniques described herein are generally related to thread migration across processing cores of a multi-core processor. Execution of a thread may be migrated from a first processing core to a second processing core. Selective state data required for execution of the thread on the second processing core can be identified and can be dynamically acquired from the first processing core. The acquired state data can be utilized by the thread executed on the second processing core.

Abstract translation: 本文描述的技术通常涉及跨多核处理器的处理核心的线程迁移。 线程的执行可以从第一处理核心迁移到第二处理核心。 可以识别在第二处理核上执行线程所需的选择状态数据，并且可以从第一处理核心动态获取。 所获取的状态数据可以由在第二处理核上执行的线程利用。

公开(公告)号：US20140181837A1

公开(公告)日：2014-06-26

申请号：US13978949

申请日：2013-03-01

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F9/46

CPC classification number: G06F9/5033 ,  G06F9/4856

Abstract: Technologies are generally provided for dynamically managing execution of sequential programs in a multi-core processing environment by dynamically hosting the data for the different dynamic program phases in the local caches of different cores. This may be achieved through monitoring data access patterns of a sequential program initially executed on a single core. Based on such monitoring, data identified as being accessed by different program phases may be sent to be stored in the local caches of different cores. The computation may then be moved from core to core based on which data is being accessed, when the program changes phase. Program performance may thus be enhanced by reducing local cache miss rates, proactively reducing the possibility of thermal hotspots, as well as by utilizing otherwise idle hardware.

Abstract translation: 通常提供技术来通过动态地托管不同核心的本地高速缓存中的不同动态程序阶段的数据来动态地管理多核处理环境中的顺序程序的执行。 这可以通过监视最初在单个核上执行的顺序程序的数据访问模式来实现。 基于这样的监视，可以发送被识别为由不同程序阶段访问的数据以被存储在不同核心的本地高速缓存中。 然后，当程序改变阶段时，计算可以基于正被访问的数据从核心移动到核心。 因此可以通过减少本地高速缓存未命中率，主动降低热点热点的可能性，以及利用其他空闲硬件来增强程序性能。

公开(公告)号：US09864709B2

公开(公告)日：2018-01-09

申请号：US14383895

申请日：2013-11-21

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F3/00 ,  G06F13/36 ,  G06F13/28 ,  G06F12/084 ,  G06F12/0817

CPC classification number: G06F13/28 ,  G06F12/0817 ,  G06F12/084 ,  G06F2212/62 ,  G06F2212/622

Abstract: Techniques described herein are generally related to data transfer in multi-core processor devices. A core of a multi-core processor device may be configured to receive a request for a data block, which may be stored in a private cache of the core. The data block in the private cache may be evaluated by a coherence module of the core to determine when the data block is in a ready state. A program slice associated with the data block may be identified by the coherence module when the data block is determined to be in an unavailable state and the identified program slice may be executed by the core to update the data block from the unavailable state to the ready state. The data block may be sent to an interconnect network in response to the received request when the stored data block is determined to be in the ready state.

公开(公告)号：US09811469B2

公开(公告)日：2017-11-07

申请号：US14407761

申请日：2014-01-29

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Sriram Vajapeyam

IPC: G06F12/08 ,  G06F12/0873 ,  G06F12/0877 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0888

CPC classification number: G06F12/0873 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0877 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/224 ,  G06F2212/283 ,  G06F2212/455 ,  G06F2212/604

Abstract: Technologies are generally described for methods and systems effective to access data in a cache. In an example, a method to access data in a cache may include processing a first request for data at a first memory address related to first data in a memory. The method may further include retrieving the first data from the memory. The method may further include storing the first data in a first cache line in the cache. The method may further include processing a second request for data at a second memory address related to second data in the memory. The method may further include retrieving the second data from the memory. The method may further include selecting a second cache line in the cache to store the second data based on the storage of the first data. The method may further include storing the second data in the second cache line.

公开(公告)号：US20150286597A1

公开(公告)日：2015-10-08

申请号：US14383895

申请日：2013-11-21

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Sriram Vajapeyam

IPC: G06F13/28 ,  G06F12/08

CPC classification number: G06F13/28 ,  G06F12/0817 ,  G06F12/084 ,  G06F2212/62 ,  G06F2212/622

Abstract: Techniques described herein are generally related to data transfer in multi-core processor devices. A core of a multi-core processor device may be configured to receive a request for a data block, which may be stored in a private cache of the core. The data block in the private cache may be evaluated by a coherence module of the core to determine when the data block is in a ready state. A program slice associated with the data block may be identified by the coherence module when the data block is determined to be in an unavailable state and the identified program slice may be executed by the core to update the data block from the unavailable state to the ready state. The data block may be sent to an interconnect network in response to the received request when the stored data block is determined to be in the ready state.

Abstract translation: 本文描述的技术通常与多核处理器设备中的数据传输有关。 多核处理器设备的核心可以被配置为接收对可能存储在核心的专用高速缓存中的数据块的请求。 专用高速缓存中的数据块可以由核心的相干模块来评估，以确定数据块何时处于就绪状态。 当数据块被确定为处于不可用状态时，可以由相干模块识别与数据块相关联的程序片，并且所识别的程序片可以由核执行以将数据块从不可用状态更新为准备 州。 当存储的数据块被确定为处于就绪状态时，数据块可以响应于接收到的请求被发送到互连网络。

公开(公告)号：US09916086B2

公开(公告)日：2018-03-13

申请号：US14648692

申请日：2013-12-04

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G11C15/00 ,  G06F12/0864

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0864 ,  G06F2212/6012 ,  G11C11/56 ,  G11C15/00 ,  Y02D10/13

Abstract: Techniques described herein are generally related to storing and retrieving data from a content-addressable memory (CAM). A data value to be stored in the CAM may be received, where the data value has two or more bits. The CAM may include a plurality of memory sets. An index corresponding to the data value may be determined. The index may be determined based on a subset of bits of the data value that correspond to an index bit set. A memory set of the CAM may be identified based on the determined index and the data value may be stored in a storage unit of the identified memory set.

公开(公告)号：US09483318B2

公开(公告)日：2016-11-01

申请号：US14371322

申请日：2013-12-20

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Sriram Vajapeyam

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5088 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5066

Abstract: Technologies are generally described for methods and systems effective to execute a program in a multi-core processor. In an example, methods to execute a program in a multi-core processor may include executing a first procedure on a first core of a multi-core processor. The methods may further include while executing the first procedure, sending a first and second instruction, from the first core to a second and third core, respectively. The instructions may command the cores to execute second and third procedures. The methods may further include executing the first procedure on the first core while executing the second procedure on the second core and executing the third procedure on the third core.

Abstract translation: 一般来说，对于在多核处理器中执行程序有效的方法和系统来描述技术。 在一个示例中，在多核处理器中执行程序的方法可以包括在多核处理器的第一核上执行第一过程。 所述方法还可以包括在执行第一过程时分别从第一核发送第一和第二指令到第二和第三核。 指令可以命令内核执行第二和第三个过程。 所述方法还可以包括在第一核上执行第一过程，同时在第二核上执行第二过程，并在第三核上执行第三过程。

公开(公告)号：US09405691B2

公开(公告)日：2016-08-02

申请号：US14369913

申请日：2013-08-12

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Sriram Vajapeyam

IPC: G06F12/00 ,  G06F12/08 ,  G06F11/30 ,  G06F11/34 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0842 ,  G06F11/3006 ,  G06F11/3404 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/62

Abstract: Techniques described herein are generally related to managing cached memory addresses in a multi-core processor device that has a plurality of cores and a plurality of caches. Communication between the plurality of caches of and a main memory may be monitored. One or more memory addresses cached by the plurality of cores may be identified based on the monitored communications. A probabilistic memory address distribution table of the locations of the one or more memory addresses cached by the plurality of core may be generated and location of a given memory address can be predicted based upon the probabilistic memory address distribution table.

Abstract translation: 本文描述的技术通常涉及在具有多个核心和多个高速缓存的多核心处理器设备中管理高速缓存的存储器地址。 可以监视多个高速缓存之间的通信和主存储器。 可以基于所监视的通信来识别由多个核心高速缓存的一个或多个存储器地址。 可以生成由多个核心缓存的一个或多个存储器地址的位置的概率存储器地址分布表，并且可以基于概率存储器地址分布表来预测给定存储器地址的位置。

公开(公告)号：US20150220369A1

公开(公告)日：2015-08-06

申请号：US14371322

申请日：2013-12-20

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Sriram Vajapeyam

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5088 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5066

Abstract: Technologies are generally described for methods and systems effective to execute a program in a multi-core processor. In an example, methods to execute a program in a multi-core processor may include executing a first procedure on a first core of a multi-core processor. The methods may further include while executing the first procedure, sending a first and second instruction, from the first core to a second and third core, respectively. The instructions may command the cores to execute second and third procedures. The methods may further include executing the first procedure on the first core while executing the second procedure on the second core and executing the third procedure on the third core.

Abstract translation: 一般来说，对于在多核处理器中执行程序有效的方法和系统来描述技术。 在一个示例中，在多核处理器中执行程序的方法可以包括在多核处理器的第一核上执行第一过程。 所述方法还可以包括在执行第一过程时分别从第一核发送第一和第二指令到第二和第三核。 指令可以命令内核执行第二和第三个过程。 所述方法还可以包括在第一核上执行第一过程，同时在第二核上执行第二过程，并在第三核上执行第三过程。