Invention Grant
- Patent Title: Semiconductor device having a reduced area and enhanced yield
- Patent Title (中): 具有减小的面积和增加的产量的半导体器件
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Application No.: US14336984Application Date: 2014-07-21
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Publication No.: US09406606B2Publication Date: 2016-08-02
- Inventor: Hiroki Fujisawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Priority: JP2013-155264 20130726
- Main IPC: G11C17/00
- IPC: G11C17/00 ; H01L23/525 ; G11C29/00 ; G11C17/16 ; H01L23/528
Abstract:
A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.
Public/Granted literature
- US20150029776A1 SEMICONDUCTOR DEVICE HAVING A REDUCED AREA AND ENHANCED YIELD Public/Granted day:2015-01-29
Information query
