Invention Grant
- Patent Title: Memory systems and methods for controlling the timing of receiving read data
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Application No.: US14280861Application Date: 2014-05-19
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Publication No.: US09411538B2Publication Date: 2016-08-09
- Inventor: Paul A. LaBerge , James B. Johnson
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F3/06 ; G06F13/16 ; G06F5/06 ; G11C7/10 ; G11C7/22
Abstract:
Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.
Public/Granted literature
- US20140258666A1 MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA Public/Granted day:2014-09-11
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