Invention Grant
- Patent Title: Top exposed semiconductor chip package
- Patent Title (中): 顶部裸露的半导体芯片封装
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Application No.: US14056047Application Date: 2013-10-17
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Publication No.: US09412684B2Publication Date: 2016-08-09
- Inventor: Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Anup Bhalla , Jun Lu , Kai Liu
- Applicant: Alpha and Omega Semiconductor Incorporated
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agent Chein-Hwa S. Tsao; Chen-Chi Lin
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/56 ; H01L23/31 ; H01L23/00
Abstract:
A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.
Public/Granted literature
- US20140035116A1 Top Exposed Semiconductor Chip Package Public/Granted day:2014-02-06
Information query
IPC分类:
