公开(公告)号：US11456596B2

公开(公告)日：2022-09-27

申请号：US17205866

申请日：2021-03-18

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Shekar Mallikarjunaswamy

IPC: H02H9/04 ,  H01L23/60 ,  H01L23/495 ,  H01L27/02 ,  H01L25/18 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/735 ,  H01L29/78 ,  H01L29/861

Abstract: A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.

公开(公告)号：US20210305406A1

公开(公告)日：2021-09-30

申请号：US17346271

申请日：2021-06-13

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L27/07

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

公开(公告)号：US10998264B2

公开(公告)日：2021-05-04

申请号：US17060083

申请日：2020-10-01

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/739 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L23/31

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

公开(公告)号：US20200381513A1

公开(公告)日：2020-12-03

申请号：US16998924

申请日：2020-08-20

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hideaki Tsuchiko

IPC: H01L29/06 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/761 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/10 ,  H01L29/735 ,  H01L29/861

Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.

公开(公告)号：US10686062B2

公开(公告)日：2020-06-16

申请号：US13892259

申请日：2013-05-11

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Madhur Bobde ,  Anup Bhalla

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/22

Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

公开(公告)号：US10388781B2

公开(公告)日：2019-08-20

申请号：US15161054

申请日：2016-05-20

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Madhur Bobde ,  Sik Lui ,  Ji Pan

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.

公开(公告)号：US20190157384A1

公开(公告)日：2019-05-23

申请号：US16258662

申请日：2019-01-27

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/0623 ,  H01L21/265 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

公开(公告)号：US10250152B2

公开(公告)日：2019-04-02

申请号：US15971629

申请日：2018-05-04

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Kuang Ming Chang ,  Lin Chen ,  Qihong Huang

IPC: H02M3/335 ,  H02M1/08 ,  H02M1/32 ,  H02M1/44 ,  H02M1/00 ,  H02M7/48 ,  H02M1/04

Abstract: A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding current to turn off the synchronous rectifier and to start the next switching cycle. At this point, the voltage across the primary switch has been discharged and the primary switch can be turned on with zero drain-to-source voltage. In other embodiments, zero voltage switching for the off-transition of the primary switch is realized by coupling a capacitor across the primary switch or by coupling a capacitor across the primary winding, or both.

公开(公告)号：US10243072B2

公开(公告)日：2019-03-26

申请号：US15971624

申请日：2018-05-04

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Madhur Bobde ,  Lingpeng Guan ,  Karthik Padmanabhan ,  Hamza Yilmaz

IPC: H01L21/84 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

公开(公告)号：US20190088740A1

公开(公告)日：2019-03-21

申请号：US16191070

申请日：2018-11-14

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hideaki Tsuchiko

IPC: H01L29/06 ,  H01L21/8222 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/761 ,  H01L27/082 ,  H01L27/088 ,  H01L21/8228 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/10 ,  H01L29/735 ,  H01L29/861 ,  H01L29/423

CPC classification number: H01L29/0649 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0821 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/063 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/8611

Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.