发明授权
US09418016B2 Method and apparatus for optimizing the usage of cache memories
有权
用于优化高速缓存存储器的使用的方法和装置
- 专利标题: Method and apparatus for optimizing the usage of cache memories
- 专利标题(中): 用于优化高速缓存存储器的使用的方法和装置
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申请号: US12974907申请日: 2010-12-21
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公开(公告)号: US09418016B2公开(公告)日: 2016-08-16
- 发明人: Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
- 申请人: Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Lowenstein Sandler LLP
- 主分类号: G06F12/02
- IPC分类号: G06F12/02 ; G06F12/08
摘要:
A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
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