发明授权
- 专利标题: Layout optimization for integrated circuit design
- 专利标题(中): 集成电路设计布局优化
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申请号: US14598773申请日: 2015-01-16
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公开(公告)号: US09418196B2公开(公告)日: 2016-08-16
- 发明人: Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Haynes and Boone, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G03F7/00
摘要:
A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
公开/授权文献
- US20150199469A1 LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN 公开/授权日:2015-07-16
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